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I find the following words a very good summary of how a memory access is conducted. Interestingly, these easy words are not from a textbook or some introductory tutorial, but from a serious academic publication (Self-Optimizing Memory Controllers: A Reinforcement Learning Approach) .

Now I quote:

Modern DRAM systems consist of dual in-line memory modules (DIMMs), which are composed of multiple DRAM chips put together to obtain a wide data interface. Each DRAM chip is organized as multiple independent memory banks. Each bank is a two-dimensional array organized as rows × columns.

Only a single row can be accessed in each bank at any given time. Each bank contains a row buffer that stores the row that can be accessed. To access a location in a DRAM bank, the memory controller must first make sure that the row is in the row buffer. An activate command brings the row whose address is indicated by the address bus from the memory array into the row buffer. Once the row is in the row buffer, the controller can issue read or write commands to access a column whose address is indicated by the address bus. Each read or write command transfers multiple columns of data, specified by a programmable burst length parameter. To access a different row, the controller must first issue a precharge command so that the data in the row buffer is written back to the memory array. After the precharge, the controller can issue an activate command to open the new row it needs to access.

The memory controller accepts cache misses and write-back requests from the processor(s) and buffers them in a memory transaction queue. The controller’s function is to satisfy such requests by issuing appropriate DRAM commands while preserving the integrity of the DRAM chips. To do so, it tracks the state of each DRAM bank (including the row buffer), each DRAM bus, and each memory request.

Quotation ends.

Mr. One Z_others